1 shows a 3-D schematic view of the different types of devices presented in this paper and a cross-sectional view of the source and drain structures. The as-written (e-beam) width of the nanowires width is 30 nm, which means that the final width is 20 nm. During processing (including gate oxidation), the width of the nanowire was reduced by 10 nm. Nanowires were fabricated with a silicon thickness ranging from 5 to 10 nm. Oxide was deposited and etched to form contact holes, and TiW + Al metallization completed the process. The source and drain regions were formed by arsenic and BF 2 ion implantation for n-channel IM and p-channel AM devices, respectively, but no source or drain implant was performed on the JL MuGFETs. The devices studied here have a gate length of 1 μ m. ) A 50-nm polysilicon layer was deposited by low-pressure chemical vapor deposition on the gate oxide and doped either by p 2+ (JL nMOS devices) or n 2+ (IM nMOS, JL pMOS, and AM pMOS). AM pMOS trigate nanowire devices were fabricated as well with unimplanted channels ( N A ∼ = 5 × 10 15 cm − 3. “Classical” IM n-channel trigate nanowire transistors were fabricated as well with a channel acceptor doping concentration of N A = 2 × 10 18 cm − 3. Gate oxidation was performed, and ion implantation was used to dope the devices uniformly n + and p + with a concentration of 1 − 2 × 10 19 cm − 3 to realize n- and p-channel devices, respectively. The SOI layer was thinned down to 10–15 nm by sacrificial oxidation and wet chemical removing process and was pat- terned to form silicon nanowires using e-beam lithography. The starting SOI film is p-type with a resistivity of 10–20 Ω D EVICE D ESIGN AND M EASUREMENTS The devices were fabricated on standard Unibond SOI wafers with a 340-nm top silicon layer and a 400-nm buried oxide. In this paper, we investigate the variation of electrical characteristics, such as the ON – OFF current and leakage current in gate-induced drain leakage (GIDL) of conventional inversion- mode (IM) nMOS, accumulation-mode (AM) pMOS, and JL pMOS and nMOS MuGFETs, with temperature. It is already known that MuGFET devices present excellent properties for high-temperature applications. ) In this paper, we investigate the temperature dependence of the electrical characteristics of JL transistors. Any increase of temperature induces variations of the electrical parameters of MOS devices (e.g., threshold voltage shift, increase of leakage current, and reduction of mobility. The absence of doping concentration gradient eliminates diffusion of impurities and the problem of sharp doping profile formation altogether.
The doping concentration is constant through the source, chan- nel, and drain. The JL transistor is a resistor with uniform doping. Recently, junctionless (JL) MuGFETs have been proposed to avoid this problem. In very-short-channel devices, the formation of ultrasharp source and drain junctions is quite a challenge and imposes drastic conditions on doping techniques and thermal budget. In a MuGFET, the gate electrode is wrapped around a silicon nanowire, forming a multigate structure with excellent control of the channel potential, which allows one to fully deplete the channel region. The International Technology Roadmap for Semiconductors predicts a 10-nm gate length with FDSOI technology in 2015 and a 7-nm gate length with double gate devices in 2018. To meet those challenges, new device architectures such as fully depleted silicon-on- insulator (FDSOI), double-gate MOSFETs, and multigate SOI MOSFETs (MuGFETs) have been proposed. I NTRODUCTION T HE creasingly SCALING difficult OF gate challenges length as in MOSFETs leakage current poses and in- short-channel effects increase due to the decreasing control efficiency of the gate on the channel.
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